Memory structures in modern integrated circuit designs may include an asynchronous clear capability to enable clearing of data within the memory structure without coordination with a clock signal used to drive the integrated circuit. However, situations can arise in which the asynchronous clear capability is not supported by either a stock memory architecture or logic synthesis software used to design the integrated circuit. For example, a field programmable gate array (FPGA) can be defined to include separate memory and logic structures, wherein the memory structure is defined to support efficient implementation of memory components. Additionally, the aforementioned FPGA may not be capable of supporting an asynchronous clear function in the memory structure.
In designing the aforementioned FPGA, the memory components associated with the asynchronous clear functionality could be defined from scratch in the logic structure of the FPGA. However, defining asynchronous memory components in the logic structure of the FPGA consumes a large amount of the available logic structure and can lead to adverse FPGA performance issues. Furthermore, when using design software to design the FPGA, extremely long design compilation times can result from explicitly defining a large number of memory components that support asynchronous clear function in the logic structure of the FPGA. Additionally, the design software may simply not be able to handle the explicit definition of a large number of asynchronous memory components in the logic structure of the FPGA.
In view of the foregoing, a solution is needed for defining asynchronous memory components in a FPGA without having to define the asynchronous memory components explicitly outside of a memory structure provided by the FPGA.